1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to data processing systems having load store units for performing data access operations.
2. Description of the Prior Art
It is known to provide data processing systems which include load store units for handling data access operations. As an example, a load instruction or a store instruction will be dispatched to the load store unit and the load store unit will then perform a data access operation in response to that load instruction or store instruction. Data access operations can sometimes have a long latency, such as when the data is not cached and the data access has to be made to a main memory or an external memory. In order to improve the efficiency of the load store unit it is known to provide the load store unit with a plurality of access slot circuits. Each of these access slot circuits can be responsible for performing processing operations in respect of a given data access instruction. In this way, a load store unit may handle multiple data access instructions in parallel.
The efficiency of the load store unit and the data processing apparatus in general may be improved if it is able to support out-of-order processing. In such out-of-order processing, data access instructions may be sent to the load store unit for execution in an order different from the order in which they appear in the execution order of the program. A consequence of such out-of-order execution is that a data access instruction appearing first in the program execution order may be bypassed by a data access instruction later in the program execution order relative to the time at which they are issued from an issue queue of data access instructions awaiting issue to the load store unit. In this circumstance, a data access instruction which due to out-of-order processing overtakes another data access instruction becomes a bypassing data access instruction. The data access instruction which is overtaken becomes a bypassed data access instruction.
While supporting out-of-order processing of data access instructions can improve instruction throughput, it can lead to difficulties. As an example, a finite number of access slot circuits will be available within the load store unit. If all of these access slot circuits are busy performing data access operations on behalf of bypassing data access instructions, then it may not be possible to issue a bypassed data access instruction to the load store unit as sufficient access slot circuits are not available to accept it. If the bypassing data access instructions have a dependency upon the bypassed data access instructions such that they cannot be retired from the access slot circuits until the bypassed data access instruction has been executed, then a deadlock situation will arise. In order to prevent such deadlocks arising, it is possible to control issue of data access instructions to the load store unit such that a minimum number of access slot circuits always remain unused so as to allow issue of a bypassed data access instruction when it is ready to be issued. In this way, it can be guaranteed that the bypassed data access instruction can be issued and accordingly a deadlock may be avoided. A problem with this approach is that the requirement to maintain a minimum number of access slot circuits empty so as to accommodate a bypassed data access instruction when it is ready to be issued results in an inefficient use of the access slot circuit resources provided, i.e. access slot circuits are provided by the system, but deliberately not used for bypassing data access instructions which are ready to be issued and instead are held empty so as to guarantee their availability for a bypassed data access instruction.